* Standard SDR Protocol Internal 4bank operation
* Voltage : VDD = 1.8V, VDDQ = 1.8V
* LVCMOS compatible I/O Interface
* Low Voltage interface to reduce I/O power
* Low Power Features - PASR(Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - DS (Drive Stre
HY5S2B6DLF-BE Datasheet (791.81 KB)
HY5S2B6DLF-BE
Hynix Semiconductor
791.81 KB
4banks x 2m x 16bits synchronous dram.
HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 .
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