HY5S2B6DLFP-SE, HY5S2B6DLF-BE Datasheet (Hynix Semiconductor)

HY5S2B6DLFP-SE, HY5S2B6DLF-BE, 4Banks x 2M x 16bits Synchronous DRAM

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Rev.

0.3 / Feb.

2005 1 1HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix Mobile SDR is suited for non-PC applica

HY5S2B6DLFP-SE Features

* Standard SDR Protocol Internal 4bank operation

* Voltage : VDD = 1.8V, VDDQ = 1.8V

* LVCMOS compatible I/O Interface

* Low Voltage interface to reduce I/O power

* Low Power Features - PASR(Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - DS (Drive Stre