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HY5S7B2ALFP-S

512M (16Mx32bit) Mobile SDRAM

HY5S7B2ALFP-S Features

* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During b

HY5S7B2ALFP-S General Description

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Nov. 2008 1 11 512Mbit (16Mx32bit) Mobile SDR Memory HY5S7B2ALF(P) Series Document Title 4Bank x 4M x 32bits Synchronous DRAM Revision History .

HY5S7B2ALFP-S Datasheet (1.84 MB)

Preview of HY5S7B2ALFP-S PDF

Datasheet Details

Part number:

HY5S7B2ALFP-S

Manufacturer:

Hynix Semiconductor

File Size:

1.84 MB

Description:

512m (16mx32bit) mobile sdram.
512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O Specification of 512M (16Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,19.

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HY5S7B2ALFP-S 512M 16Mx32bit Mobile SDRAM Hynix Semiconductor

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