HY5S7B2ALFP-S - 512M (16Mx32bit) Mobile SDRAM
and is subject to change without notice.
Hynix does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev 1.2 / Nov.
2008 1 11 512Mbit (16Mx32bit) Mobile SDR Memory HY5S7B2ALF(P) Series Document Title 4Bank x 4M x 32bits Synchronous DRAM Revision History
HY5S7B2ALFP-S Features
* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During b
