HY5W6B6DLF Datasheet - Hynix

HY5W6B6DLF 4 Bank x 1 M x 16 Bit Synchronous DRAM

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / Feb. 2004 1 Preliminary HY5W6B6DLF(P)-xE 4Banks x1M x 16bits Synchronous DRAM DESCRIPTION The Hynix Low Power SDRAM is suited for non-PC applic.

HY5W6B6DLF Features

* Standard SDRAM Protocol Internal 4bank operation

* Power Supply Voltage : VDD = 2.5V, VDDQ = 2.5V LVCMOS compatible I/O Interface Low Voltage interface to reduce I/O power Low Power Features - PASR(Partial Array Self Refresh) - AUTO TCSR (Temperature Compensated Self Refresh) - DS (Drive Streng

HY5W6B6DLF Datasheet (330.15 KB)