VDD=1.8V ± 0.1V, VDDQ=1.8V ± 0.1V Single ended READ Strobe (RDQS) per byte Single ended WRITE Strobe (WDQS) per byte Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Calibrated output drive Differential clock inputs (CK and CK#) Commands entered on each positive CK edge RDQS edge-aligned with data for READs; with WDQS center-aligned with data for WRITEs Four interna.