HY5RS123235BFP Datasheet - Hynix Semiconductor

HY5RS123235BFP 512Mbit GDDR3 SDRAM

and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2 / Jul. 2007 1 HY5RS123235BFP Revision History Revision No. History Draft Date Remark 0.0 Defined target spec. Apr. 2006 P.

HY5RS123235BFP Features

* 2.05V/ 1.8V power supply supports (For more detail, Please see the Table 12 on page 43)

* Single ended READ Strobe (RDQS) per byte

* Single ended WRITE Strobe (WDQS) per byte

* Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycl

HY5RS123235BFP-HynixSemiconductor.pdf