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ICS487-25 Quad PLL

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Description

www.DataSheet4U.com ICS487-25 Quad PLL for DTV .
The ICS487-25 generates five high-quality, high-frequency clock outputs.

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Datasheet Specifications

Part number
ICS487-25
Manufacturer
ICS
File Size
173.72 KB
Datasheet
ICS487-25_ICS.pdf
Description
Quad PLL

Features

* Packaged in 16-pin TSSOP Available in Pb-free packaging Replaces multiple crystals and oscillators Input crystal or clock frequency of 27 MHz Zero ppm frequency synthesis error Duty cycle of 45/55 Operating voltage of 3.

Applications

* Using ICS’ patented Phase Locked Loop (PLL) techniques, the device runs from a lower frequency crystal or clock input. Because there is zero ppm frequency synthesis error on the audio clocks, the audio will remain locked to the video. Block Diagram VDD 3 2 S1:0 PLL1 ACLK 20M PLL2 48M PLL3 33.0M

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