IDT72V271LA Description
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 IDT72V261LA 32,768 x 9 IDT72V271LA LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15.IDT72V271LA Features
* Choose among the following memory organizations: IDT72V261LAIDT72V271LA Applications
* that need to buffer large amounts of data. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) inpu
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