Description
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 IDT72V261LA 32,768 x 9 IDT72V271LA LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15.
The IDT72V261LA/72V271LA are functionally compatible versions of the IDT72261/72271 designed to run off a 3.
Features
* Choose among the following memory organizations: IDT72V261LA
* 16,384 x 9 IDT72V271LA
* 32,768 x 9
* Pin-compatible with the IDT72V281/72V291 and IDT72V2101/ 72V2111SuperSync FIFOs
* Functionally compatible with the 5 Volt IDT72261/72271 family
* 10
Applications
* that need to buffer large amounts of data. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) inpu