Datasheet Specifications
- Part number
- IDT72V261LA
- Manufacturer
- IDT
- File Size
- 202.74 KB
- Datasheet
- IDT72V261LA-IDT.pdf
- Description
- CMOS FIFO memories
Description
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 IDT72V261LA 32,768 x 9 IDT72V271LA LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15.Features
* Choose among the following memory organizations: IDT72V261LAApplications
* that need to buffer large amounts of data. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) inpuIDT72V261LA Distributors
📁 Related Datasheet
📌 All Tags