Datasheet Specifications
- Part number
- IDT72V265LA
- Manufacturer
- Integrated Device Tech
- File Size
- 181.52 KB
- Datasheet
- IDT72V265LA_IntegratedDeviceTechnology.pdf
- Description
- CMOS FIFO memories
Description
3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18 .
Features
* IDT72V255LA IDT72V265LAApplications
* that need to buffer large amounts of data. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) inpIDT72V265LA Distributors
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