* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Burst sequence control using MODE input
* Three chip enable option for simple depth ex- pansion and address pipelini
IS61LPS204818B Datasheet (1.20 MB)
IS61LPS204818B
ISSI
1.20 MB
36mb single cycle deselect static ram.
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CY.
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