Datasheet Details
| Part number | IS61QDP2B41M18C |
|---|---|
| Manufacturer | ISSI |
| File Size | 858.94 KB |
| Description | 18Mb QUADP SYNCHRONOUS SRAM |
| Datasheet |
 IS61QDP2B41M18C-ISSI.pdf
|
| Part number | IS61QDP2B41M18C |
|---|---|
| Manufacturer | ISSI |
| File Size | 858.94 KB |
| Description | 18Mb QUADP SYNCHRONOUS SRAM |
| Datasheet |
IS61QDP2B41M18C-ISSI.pdf
|
1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and cont
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