Description
IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.0 Cycle Read Latency) JANUARY 2015 .
The 36Mb IS61QDP2B41M36A/A1/A2 and IS61QDP2B42M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices.
Features
* 1Mx36 and 2Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Separate independent read and write ports with concurrent read and write operations.
* Synchronous pipeline read with late write operation.
* Double Data Rate (DDR) interfac
Applications
* where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance