Description
IS61QDPB24M18C/C1/C2 IS61QDPB22M36C/C1/C2 4Mx18, 2Mx36 72Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) APRIL 2018 .
at page 6 for each ODT option.
Features
* 2Mx36 and 4Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Separate independent read and write ports with concurrent read and write operations.
* Max. 450 MHz clock for high bandwidth
* Synchronous pipeline read with EARLY write ope
Applications
* where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance
