IS62WV12816DBLL Datasheet | ISSI

FEATURES - High-speed access time: 35ns, 45ns, 55ns - CMOS low power operation - 36 m W (typical) operating - 9 µW (typical) CMOS standby - TTL patible interface levels - Single power supply - 1.8V ± 10% Vdd (IS62/65WV12816DALL) - 2.5V--3.6V Vdd (IS62/65WV12816DBLL) - Fully static operation: no clock or refresh required - Three state outputs - Data control for upper and lower bytes - Industrial and Autotmovie temperature support - 2CS Option Available - Lead-free available FUNCTIONAL BLOCK DIAGRAM DESCRIPTION The ISSI IS62/65WV12816DALL/DBLL are high-speed, 2M bit static RAMs organized as 128K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is low (deselected) or when CS1 is low, CS2 is high and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62/65WV12816DALL/DBLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44Pin TSOP (TYPE II). A0-A16 DECODER 128K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CS2 CS1 OE WE UB LB CONTROL CIRCUIT Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and...