Datasheet4U Logo Datasheet4U.com

IS41C8512 512K x 8 (4-MBIT) DYNAMIC RAM

IS41C8512 Description

IS41C8512 IS41LV8512 .EATURES www.datasheet4u.com 512K x 8 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE Extended Data-Out (EDO) Page Mode access cycle TTL.
The 1+51 IS41C8512 and IS41LV8512 is a 524,288 x 8-bit high-performance CMOS Dynamic Random Access Memories.

IS41C8512 Applications

* The IS41C8512 is packaged in a 28-pin 400mil SOJ and 400mil TSOP-2. KEY TIMING PARAMETERS Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. EDO Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -35 35 10 18 12 60 -50 50 14 25 20

📥 Download Datasheet

Preview of IS41C8512 PDF
datasheet Preview Page 2 datasheet Preview Page 3

📁 Related Datasheet

  • IS41C85120 - 512K x 8 (4-MBIT) DYNAMIC RAM (Integrated Silicon Solution)
  • IS41C85120A - 512K x 8 (4-MBIT) DYNAMIC RAM (Integrated Silicon Solution)
  • IS41C85125 - 512K x 8 (4-MBIT) DYNAMIC RAM (Integrated Silicon Solution)
  • IS41C85125A - 512K x 8 (4-MBIT) DYNAMIC RAM (Integrated Silicon Solution)
  • IS41C8200 - 2M x 8 (16-MBIT) DYNAMIC RAM (Integrated Silicon Solution)
  • IS41C8205 - 2M x 8 (16-MBIT) DYNAMIC RAM (Integrated Silicon Solution)
  • IS41C16100 - 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE (Integrated Silicon Solution)
  • IS41C16100S - 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE (Integrated Silicon Solution)

📌 All Tags

512K 4-MBIT DYNAMIC RAM Integrated Circuit Solution
Integrated Circuit Solution IS41C8512-like datasheet