ICS91305 Datasheet (Integrated Circuit Systems) - High Performance Communication Buffer

ICS91305, High Performance Communication Buffer

The ICS91305 is a high performance, low skew, low jitter clock driver.

It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal.

It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MH

ICS91305 Features

* Zero input - output delay Frequency range 10 - 133 MHz (3.3V) 5V tolerant input REF High loop filter bandwidth ideal for Spread Spectrum applications. Less than 200 ps Jitter between outputs Skew controlled out