ICS93705 - DDR Phase Lock Loop Zero Delay Clock Buffer
ICS93705 Features
* Low skew, low jitter PLL clock driver
* I2C for functional and output control
* Feedback pins for input to output synchronization
* Spread Spectrum tolerant inputs
* 3.3V tolerant CLK_INT input Switching Characteristics:
* PEAK - PEAK jitter (66MHz)
