IDT72V36100 - CMOS FIFO

Integrated Device Tech

Datasheet Details

Choose among the following memory organizations: IDT72V36100 ⎯ 65,536 x 36 IDT72V36110 ⎯ 131,072 x 36.
Higher density, 2Meg and 4Meg SuperSync II FIFOs.
Up to 166 MHz Operation of the Clocks.
User selectable Asynchronous read and/or write ports (PBGA Only).
User selectable input and output port bus-sizing - x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out.
Big-Endian/Little-Endian user selectab.

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