ICS854S204I - LVPECL FANOUT BUFFER

Product Overview

Integrated Device Technology

Datasheet Details

Part number	ICS854S204I
Manufacturer	Integrated Device Technology
File Size	394.27 KB
Description	LVPECL FANOUT BUFFER
Datasheet	ICS854S204I Datasheet
Additional preview pages of the ICS854S204I datasheet.

Product details

Description

The ICS854S204I is a low skew, high performance IC S dual, programmable 1-to-2 Differential-to-LVDS, HiPerClockS™ LVPECL Fanout Buffer and a member of the HiPerClock S™ family of High Performance Clock Solutions from IDT.

Features

Two programmable differential LVDS or LVPECL output banks.
Two differential clock input pairs.
PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML.
Maximum output frequency: 3GHz.
Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx inputs.
Output skew: 15ps (maximum).
Bank skew: 15ps (maximum).
Propagation delay: 500ps (maximum).
Additive.

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Published: May 13, 2010 |