Datasheet4U Logo Datasheet4U.com

ICS854S204I Datasheet - Integrated Device Technology

ICS854S204I LVPECL FANOUT BUFFER

The ICS854S204I is a low skew, high performance IC S dual, programmable 1-to-2 Differential-to-LVDS, HiPerClockS™ LVPECL Fanout Buffer and a member of the HiPerClock S™ family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels. Wi.

ICS854S204I Features

* Two programmable differential LVDS or LVPECL output banks

* Two differential clock input pairs

* PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML

* Maximum output frequency: 3GHz

* Translates any single ended in

ICS854S204I Datasheet (394.27 KB)

Preview of ICS854S204I PDF
ICS854S204I Datasheet Preview Page 2 ICS854S204I Datasheet Preview Page 3

Datasheet Details

Part number:

ICS854S204I

Manufacturer:

Integrated Device Technology

File Size:

394.27 KB

Description:

Lvpecl fanout buffer.

📁 Related Datasheet

ICS854S202I Differential-to-LVDS Multiplexer (IDT)

ICS854S202I-01 Differential-To-LVDS Multiplexer (Renesas)

ICS854S296I-33 LVDS Programmable Delay-Line (Renesas)

ICS854S006I Differential-to-LVDS Fanout Buffer (IDT)

ICS854S013 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER (Integrated Device Technology)

ICS854S01I 2:1 Differential-to-LVDS Multiplexer (Renesas)

ICS854S01I 2:1 Differential-to-LVDS Multiplexer (IDT)

ICS854S054I 4:1 Differential-to-LVDS Clock Multiplexer (Renesas)

TAGS

ICS854S204I LVPECL FANOUT BUFFER Integrated Device Technology

ICS854S204I Distributor