IDT71V3556S Datasheet - Integrated Device Technology

3.3V Synchronous ZBT SRAMs

IDT71V3556S Features

* 128K x 36, 256K x 18 memory configurations Supports high performance system speed - 200 MHz (3.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin Po

IDT71V3556S General Description

The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signal.

IDT71V3556S Datasheet (477.21 KB)

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IDT71V3556S

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Integrated Device Technology

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477.21 KB

Description:

3.3v synchronous zbt srams.
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs x x IDT71V3556S IDT71V3558S IDT71V3556SA IDT71V3558SA Feat.

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IDT71V3556S 3.3V Synchronous ZBT SRAMs Integrated Device Technology

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IDT71V3556S Features

IDT71V3556S General Description

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