IDT71V3556SA, IDT-71V Datasheet - Integrated Device Technology

IDT71V3556SA 3.3V Synchronous ZBT SRAMs

The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signal.

IDT71V3556SA Features

* 128K x 36, 256K x 18 memory configurations Supports high performance system speed - 200 MHz (3.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin Po

IDT-71V-3556S.pdf