QS5LV91955J Overview
QS5LV919 3.3V operation JEDEC patible LVTTL level outputs Clock inputs are 5V tolerant < 300ps output skew, Q0 Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable.
QS5LV91955J Details
| Part number | QS5LV91955J |
|---|---|
| Datasheet | QS5LV91955J_IntegratedDeviceTechnology.pdf |
| File Size | 98.35 KB |
| Manufacturer | Integrated Device Technology |
| Description | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER |
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