* 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single R/W (
IS61NLP25632 Datasheet (157.01 KB)
IS61NLP25632
Integrated Silicon Solution Inc
157.01 KB
256k x 32/ 256k x 36 and 512k x 18 pipeline no wait state bus sram.
IS61NP25632 IS61NP25636 IS61NP51218 IS61NLP25632 IS61NLP25636 IS61NLP51218
256K x 32, 256K x 36 and 512K x 18 PIPELINE 'NO WAIT' STATE BUS SRAM
ISSI
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