Description
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A 1Mb x 36 and 2Mb x 18 36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEBRUARY 2012 .
The 36 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait'.
Features
* 100 percent bus utilization
* No wait cycles between Read and Write
* Internal self-timed write cycle
* Individual Byte Write Control
* Single R/W (Read/Write) control pin
* Clock controlled, registered address,
data and control
* Interleaved
