IS61NLP204818A Features
* 100 percent bus utilization
* No wait cycles between Read and Write
* Internal self-timed write cycle
* Individual Byte Write Control
* Single R/W (Read/Write) control pin
* Clock controlled, registered address, data and control
* Interleaved
IS61NVP204818A_IntegratedSiliconSolution.pdf
Datasheet Details
IS61NLP204818A, IS61NVP204818A
Integrated Silicon Solution
168.59 KB
36mb state bus sram.
This datasheet PDF includes multiple part numbers: IS61NLP204818A, IS61NVP204818A.
Please refer to the document for exact specifications by model.
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