IS61DDP2B22M18A2 - 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM
* 1Mx36 and 2Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Common I/O read and write ports.
* Synchronous pipeline read with self-timed late write operation.
* Double Data Rate (DDR) interface for read and write input ports.
*
