IS61DDPB44M18B2 - 72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
* 2Mx36 and 4Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Common I/O read and write ports.
* Synchronous pipeline read with self-timed late write operation.
* Double Data Rate (DDR) interface for read and write input ports.
*
