Datasheet Details
- Part number
- M2020-2021
- Manufacturer
- Integrated Circuit Systems
- File Size
- 431.78 KB
- Datasheet
- M2020-2021_IntegratedCircuitSystems.pdf
- Description
- VCSO BASED CLOCK PLL
M2020-2021 Description
Integrated Circuit Systems, Inc.Product Data Sheet M2020/21 VCSO BASED CLOCK PLL GENERAL .
The M2020/21 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency trans.
M2020-2021 Features
* Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz)
* Output frequencies of 15 to 700 MHz
* LVPECL clock output (CML and LVDS options available)
* Reference clock inputs support differential LVDS, LVPE
M2020-2021 Applications
* to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz. When LOL is to be used for system health monitoring, the phase detector frequency should be 5MHz or greater. Low phase detector frequencies ma
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