IDT71V3556S Description
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs x x IDT71V3556S IDT71V3558S IDT71V3556SA IDT71V3558SA Feat.
The IDT71V3556/58 are 3.
IDT71V3556S Features
* 128K x 36, 256K x 18 memory configurations Supports high performance system speed - 200 MHz (3.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin Po
IDT71V3556S Applications
* 4-word burst capability (interleaved or linear) Individual byte write (BW 1 - BW4) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply (±5%), 3.3V I/O Supply (VDDQ) Optional- Boundary Scan JTAG Interface (IEEE 1149.1 compliant) Packaged in a JEDEC standard 100-pi
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