IDT71V65603 Description
256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ .IDT71V65603 Features
* 256K x 36, 512K x 18 memory configurations Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin PosIDT71V65603 Applications
* 4-word burst capability (interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply (±5%) 3.3V I/O Supply (VDDQ) Power down controlled by ZZ input Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (T
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