CD4015BMS - CMOS Dual 4-Stage Static Shift Register
of ‘B’ Series CMOS Devices” Functional Diagram VDD 16 DATA A CLOCK A RESET A 7 9 6 4 STAGE 5 4 3 10 DATA B 15 1 14 RESET B 4 STAGE 13 12 Q2B 11 Q3B 2 Q4B 8 VSS Q1A Q2A Q3A Q4A Q1B Applications * Serial-Input/Parallel-Output Data Queueing * Serial to Parallel Data Conversion
CD4015BMS Features
* High-Voltage Type (20V Rating)
* Medium Speed Operation 12MHz (typ.) Clock Rate at VDD - VSS = 10V
* Fully Static Operation
* 8 Master-Slave Flip-Flops Plus Input and Output Buffering
* 100% Tested For Quiescent Current at 20V
* 5V, 10V and 15V Param
