CD4027BMS - CMOS Dual J-K Master-Slave Flip-Flop

Intersil Corporation

CD4027BMS Datasheet Preview — Preview of CD4027BMS PDF

Datasheet Details

Part number	CD4027BMS
Manufacturer	Intersil Corporation
File Size	72.40 KB
Description	CMOS Dual J-K Master-Slave Flip-Flop
Datasheet	CD4027BMS_IntersilCorporation.pdf

CD4027BMS Product details

Description

of ‘B’ Series CMOS Devices” Q2 1 Q2 2 CLOCK 2 3 RESET 2 4 K2 5 J2 6 SET 2 7 VSS 8 16 VDD 15 Q1 14 Q1 13 CLOCK 1 12 RESET 1 11 K1 10 J1 9 SET 1 Functional Diagram SET 1 9 VDD 16 J1 10 K1 11 CLOCK1 13 F/F1 15 Q1 14 Q1 Applications Registers, Counters, Control Circuits RESET1 12 SET2 J2 K2 7 6 5 3 F/F2 2 Q2 1 Q2 Description CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K masterslave ﬂip-ﬂops.Each ﬂip-ﬂop has provisions f

Features

High Voltage Type (20V Rating).
Set - Reset Capability.
Static Flip-Flop Operation - Retains State Indeﬁnitely with Clock Level Either “High” or “Low”.
Medium Speed Operation - 16MHz (typ. ) Clock Toggle Rate at 10V.
Standardized Symmetrical Output Characteristics.
100% Tested For Quiescent Current at 20V.
Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; - 100nA at 18V and +25oC.
Noise Margin (Over Fu.

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Published: Mar 23, 2005 |