HSP50016 Datasheet (Intersil Corporation)

HSP50016, Digital Down Converter

NAME VCC GND DATA0-15 CLK RESET TYPE I I I +5V Power.

Ground.

Input Data Bus.

Selectable between two's complement and offset binary.

DATA0 is the LSB.

Clock for input data bus.

fS is the frequency of CLK, which is also the input sample rate.

RESET initializes the internal state of the DDC.

During RE

HSP50016 Data Sheet February 1999 File Number 3288.6 Digital Down Converter The Digital Down Converter (DDC) is a single chip synthesizer, quadrature mixer and lowpass ﬁlter.

Its input data is a sampled data stream of up to 16 bits in width and up to a 75 MSPS data rate.

The DDC performs down conversion, narrowband low pass ﬁltering and decimation to produce a baseband signal.

The internal synthesizer can produce a variety of signal formats.

They are: CW, frequency hopped, linear FM up chirp, a

HSP50016 Features

* 75 MSPS Input Data Rate

* 16-Bit Data Input; Offset Binary or 2’s Complement Format

* Spurious Free Dynamic Range Through Modulator >102dB

* Frequency Selectivity: