MachXO3
Lattice
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MachXO - FPGA
(Lattice)
MachXO Family Data Sheet
DS1002 Version 03.0, June 2013
MachXO Family Data Sheet Introduction
June 2013
Features
Non-volatile, Infinitely Reconfig.
MachXO2 - FPGA
(Lattice)
MachXO2™ Family Data Sheet
DS1035 Version 3.3, March 2017
MachXO2 Family Data Sheet Introduction
May 2016
Data Sheet DS1035
Features
Flexible Lo.
MACH1 - High-Performance EE CMOS Programmable Logic
(Lattice)
MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmable Logic
FEATURES
x x x x x x
x x x x x x
x
High-performance electrically-erasable C.
MACH110-12 - High-Density EE CMOS Programmable Logic
(Advanced Micro Devices)
FINAL
COM’L: -12/15/20
IND: -14/18/24
MACH110-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
s 44 Pins s 32 Macrocell.
MACH110-12 - High-Density EE CMOS Programmable Logic
(Lattice)
FINAL
COM’L: -12/15/20
IND: -14/18/24
MACH110-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
s 44 Pins s 32 Macrocell.
MACH110-15 - High-Density EE CMOS Programmable Logic
(Advanced Micro Devices)
FINAL
COM’L: -12/15/20
IND: -14/18/24
MACH110-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
s 44 Pins s 32 Macrocell.
MACH110-15 - High-Density EE CMOS Programmable Logic
(Lattice)
FINAL
COM’L: -12/15/20
IND: -14/18/24
MACH110-12/15/20
High-Density EE CMOS Programmable Logic
Lattice Semiconductor
DISTINCTIVE CHARACTERISTICS
.
MACH110-20 - High-Density EE CMOS Programmable Logic
(Advanced Micro Devices)
FINAL
COM’L: -12/15/20
IND: -14/18/24
MACH110-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
s 44 Pins s 32 Macrocell.
MACH110-20 - High-Density EE CMOS Programmable Logic
(Lattice)
FINAL
COM’L: -12/15/20
IND: -14/18/24
MACH110-12/15/20
High-Density EE CMOS Programmable Logic
Lattice Semiconductor
DISTINCTIVE CHARACTERISTICS
.
MACH111 - High-Performance EE CMOS Programmable Logic
(Lattice Semiconductor)
MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmable Logic
FEATURES
x High-performance electrically-erasable CMOS PLD families x 32 to 128.