P2S28D30CTP Datasheet (MIRA) - (P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM

P2S28D30CTP, (P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM

P2S28D30CTP is a 4-bank x 4,194,304-word x 8bit,P2S28D40CTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

All control and address signals www.DataSheet4U.com are referenced to the rising edge of CLK.

Input data is registered on both edges of data str

P2S28D30CTP Features

* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each