P2S28D30CTP (P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM

MIRA

Description

Deutron Electronics Corp.P2S28D30/40CTP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice..
P2S28D30CTP is a 4-bank x 4,194,304-word x 8bit,P2S28D40CTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 inter.

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Datasheet Specifications

Part number: P2S28D30CTP
Manufacturer: MIRA
File Size: 301.58 KB
Datasheet: P2S28D30CTP_MIRA.pdf
Description: (P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM

Features

* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each

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P2S28D30CTP P2S28D30CTP P2S28D40CTP 128M Double Data Rate Synchronous DRAM MIRA

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