* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each
P2S28D40CTP Datasheet (301.58 KB)
P2S28D40CTP
MIRA
301.58 KB
(p2s28d30ctp / p2s28d40ctp) 128m double data rate synchronous dram.
Deutron Electronics Corp.
P2S28D30/40CTP
128M Double Data Rate Synchronous DRAM
PRELIMINARY
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