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MAX3872 - Multirate Clock and Data Recovery

MAX3872 Description

19-2709; Rev 1; 5/03 KIT ATION EVALU E L B A IL AVA Multirate Clock and Data Recovery with Limiting Amplifier General .
Features o Multirate Data Input: 2.

MAX3872 Features

* o Multirate Data Input: 2.667Gbps (FEC), 2.488Gbps, 1.244Gbps, 622.08Mbps, 155.52Mbps, 1.25Gbps/2.5Gbps (Ethernet) o Reference Clock Not Required for Data Acquisition o Exceeds ANSI, ITU, and Bellcore SONET/SDH Jitter Specifications o 2.7mUIRMS Jitter Generation o 10mVP-P Input Sensitivity Without T

MAX3872 Applications

* Without using an external reference clock, the fully integrated phaselocked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by the recovered clock, providing a clean data output. An additional serial input (SLBI±) is available for system

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