Description
PIC16F13145 Family Full-.
Features
* C Compiler Optimized RISC Architecture
* Operating Speed:
* DC-32 MHz clock input
* 125 ns minimum instruction time
* 16-Level Deep Hardware Stack
* Low-Current Power-on Reset (POR)
* Configurable Power-up Timer (PWRT)
* Brown-out Res
Applications
* The CLB is comprised of 32 individual logic elements. Each logic element’s Look Up Table (LUT) based design offers vast customization options, and CPU-independent operation improves the response time and power consumption. This product family is available in 8, 14, and 20-pin packages and offers up
