MT48LC8M32B2 Datasheet (Micron Technology)

MT48LC8M32B2, SYNCHRONOUS DRAM

The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits.

It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).

Each of the www.DataSheet4U.com 67,108,864-bit bank

MT48LC8M32B2 Features

* PC100 functionality

* Fully synchronous; all signals registered on positive edge of system clock

* Internal pipelined operation; column address can www.DataSheet4U.com be changed every clock cycle

* Internal banks for hiding row access/precharge

* Programmab