M2S56D20TP-75 - 256M Double Data Rate Synchronous DRAM
M2S56D20TP is a 4-bank x 16777216-word x 4-bit, M2S56D30TP is a 4-bank x 8388608-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface.
All control and address signals are referenced to the rising edge of CLK.
Input data is registered on both edges of data strobe, and output data an
M2S56D20TP-75 Features
* - Vdd=Vddq=2.5v±0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each po
