M2V28S40ATP Datasheet, Dram, Mitsubishi

M2V28S40ATP Features

• Dram M2V28S20/30/40ATP ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time Row to Column Delay Access Time from CLK Ref/Active Command Period Operation Current (Max.) (Single Bank) (Max.) (Min

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M2V28S40ATP

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Mitsubishi

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📄 Datasheet

Description:

128m synchronous dram. M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30ATP is organized as 4-b

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M2V28S40ATP

Mitsubishi

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