M2V28S30TP
Mitsubishi
639.70kb
128m synchronous dram. M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30TP is organized as 4-ban
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M2V28S30ATP - 128M Synchronous DRAM
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M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
SD.
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M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
SD.
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MITSUBISHI LSIs
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L M2V28S40TP-7,-7L,-8,-8L
(4-BANK x 8,.
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M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
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M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L M2V28S40TP-7,-7L,-8,-8L
(4-BANK x 8,.
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