M2V28S40TP 128M Synchronous DRAM

Mitsubishi

Description

128M Synchronous DRAM SDRAM (Rev.1.0E) Jun.'99 MITSUBISHI LSIs M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L M2V28S40TP-7,-7L,-8,-8L (4-BANK x 8,.
M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30TP is organized as 4-bank x 4,194,304-wor.

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Datasheet Specifications

Part number: M2V28S40TP
Manufacturer: Mitsubishi
File Size: 639.70 KB
Datasheet: M2V28S40TP_MitsubishiElectricSemiconductor.pdf
Description: 128M Synchronous DRAM

Features

* M2V28S20/30/40TP ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time Row to Column Delay Access Time from CLK Ref/Active Command Period Operation Current (Max. ) (Single Bank) (Max. ) (Min. ) (Min. ) (Min. ) (Max. ) (CL=3) (Min. ) V28S20 V28S30 V28S40 Icc6 Self Refresh Current -6 7.5ns 45ns 20ns 5.4ns 67.5ns

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M2V28S40TP 128M Synchronous DRAM Mitsubishi

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