M5M4V64S30ATP-12 - 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

Mitsubishi

Datasheet Details

Part number	M5M4V64S30ATP-12
Manufacturer	Mitsubishi
File Size	1.07 MB
Description	64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Datasheet	M5M4V64S30ATP-12_MitsubishiElectricSemiconductor.pdf

The M5M4V64S30ATP is a 4-bank x 2097152-word x 8-bit Synchronous DRAM, with LVTTL interface.

- Single 3.3v±0.3v power supply - Clock frequency 125MHz / 100MHz / 83MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles /64ms - Column address A0-A8 - LVTTL Interfac.

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Published: Apr 26, 2005 |