20N03HL Datasheet (Motorola)

20N03HL, MTD20N03HL

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTD20N03HDL/D Designer's HDTMOS E-FET .™ High Density Power FET DPAK for Surface Mount N Channel Enhancement Mode Silicon Gate This advanced HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes.

This new energy efficient design also offers a drain to source diode with a fast recovery time.

Designed for low voltage, high speed switching applications in power sup

20N03HL Features

* d by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed rea