* d by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed rea
20N03HL
Motorola
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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTD20N03HDL/D Designer's HDTMOS E-FET .™ High Density Power FET DPAK for Surface Moun.
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