MOTOROLA SEMICONDUCTOR TECHNICAL DATA CMOS MSI Quad R S Latches The MC14043B and MC14044B quad R S latches are constructed with MOS P channel and N channel enhancement mode devices in a single monolithic structure.
Each latch has an independent Q output and set and reset inputs.
The Q outputs are gated through three state buffers having a common enable input.
The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disc
