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MCM63P531 32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM63P531 Description

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63P531/D Advance Information MCM63P531 32K x 32 Bit Pipelined BurstRAM™ Synchrono.
Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE, or chip deselect cycl.

MCM63P531 Features

* e b Write Byte c Write Byte d Write All Bytes Write All Bytes SGW H H H H H H H L SW H L L L L L L X SBa X H L H H H L X SBb X H H L H H L X SBc X H H H L H L X SBd X H H H H L L X DC ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VDD

MCM63P531 Applications

* Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and Linear Burst Order

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Datasheet Details

Part number
MCM63P531
Manufacturer
Motorola
File Size
334.49 KB
Datasheet
MCM63P531_MotorolaInc.pdf
Description
32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

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32K Bit Pipelined BurstRAM Synchronous Fast Static RAM Motorola
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