MCM63P531 Datasheet - Motorola

MCM63P531 32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE, or chip deselect cycle. Synchronous Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (exception * chip deselect does not occur when ADSP is .

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63P531/D Advance Information MCM63P531 32K x 32 Bit Pipelined BurstRAM™ Synchronous Fast Static RAM The MCM63P531 is a 1M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, and Pentium™ microprocessors. It is organized as 32K words of 32 bits each, fabricated using high performance silicon gate CMOS technology. This device integrates input registers, .

MCM63P531 Features

* e b Write Byte c Write Byte d Write All Bytes Write All Bytes SGW H H H H H H H L SW H L L L L L L X SBa X H L H H H L X SBb X H H L H H L X SBc X H H H L H L X SBd X H H H H L L X DC ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VDD

MCM63P531_MotorolaInc.pdf

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Datasheet Details

Part number:

MCM63P531

Manufacturer:

Motorola

File Size:

334.49 KB

Description:

32k x 32 bit pipelined burstram synchronous fast static ram.

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MCM63P531 MCM63P531 32K Bit Pipelined BurstRAM Synchronous Fast Static RAM Motorola

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