MCM63P631A Datasheet - Motorola

MCM63P631A 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Pin Locations 85 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, is used to latch a new external address. Used to initiate a READ, WRITE or chip deselect. Synchronous Address Status Processor: Initiates READ or chip deselect cycle (exception * chip dese.

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63P631A/D Product Preview MCM63P631A 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P631A is a 2M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, and Pentium™ microprocessors. It is organized as 64K words of 32 bits each. This device integrates input registers, an output register, a 2 bit address counter, and high spee.

MCM63P631A Features

* rite Byte c Write Byte d Write All Bytes Write All Bytes SGW H H H H H H H L SW H L L L L L L X SBa X H L H H H L X SBb X H H L H H L X SBc X H H H L H L X SBd X H H H H L L X MCM63P631A 6 MOTOROLA FAST SRAM ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Power Supply Voltage Voltage Relative

MCM63P631A Datasheet (228.58 KB)

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Datasheet Details

Part number:

MCM63P631A

Manufacturer:

Motorola

File Size:

228.58 KB

Description:

64k x 32 bit pipelined burstram synchronous fast static ram.

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MCM63P631A 64K Bit Pipelined BurstRAM Synchronous Fast Static RAM Motorola

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