MCM63P631 Datasheet (Motorola) - 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM63P631, 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Pin Locations 85 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, is used to latch a new external address.

Used to initiate a READ, WRITE or chip deselect.

Synchronous Address Status Processor: Initiates READ or chip deselect cycle (exception * chip dese

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63P631/D Advance Information MCM63P631 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P631 is a 2M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, and Pentium™ microprocessors.

It is organized as 64K words of 32 bits each.

This device integrates input registers, an output register, a 2 bit address counter, and high spe

MCM63P631 Features

* rite All Bytes Write All Bytes SGW H H H H H H H L SW H L L L L L L X SBa X H L H H H L X SBb X H H L H H L X SBc X H H H L H L X SBd X H H H H L L X MCM63P631 6 MOTOROLA FAST SRAM ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except