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MCM63P818 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM63P818 Description

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63P736/D Product Preview 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronou.
Pin Locations 4B Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new.

MCM63P818 Features

* us Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: these pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte

MCM63P818 Applications

* Synchronous design allows precise cycle control with the use of an external clock (K). Addresses (SA), data inputs (DQx), and all control signals except output enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled through positive
* edge
* triggered noninver

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Datasheet Details

Part number
MCM63P818
Manufacturer
Motorola
File Size
315.65 KB
Datasheet
MCM63P818_MotorolaInc.pdf
Description
128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

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128K and 256K Bit Pipelined BurstRAM Synchronous Fast Static RAM Motorola
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